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Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.
The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com
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HM62V8100I Series
Wide Temperature Range Version 8 M SRAM (1024-kword x 8-bit)
ADE-203-1278B (Z) Rev. 1.0 Mar. 12, 2002
Description
The Hitachi HM62V8100I Series is 8-Mbit static RAM organized 1,048,576-word x 8-bit. HM62V8100I Series has realized higher density, higher performance and low power consumption by employing Hi-CMOS process technology. It offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in 48 bumps chip size package with 0.75 mm bump pitch or standard 44-pin TSOP II for high density surface mounting.
Features
* * * Single 3.0 V supply: 2.7 V to 3.6 V Fast access time: 55 ns (Max) Power dissipation: Active: 6.0 mW/MHz (Typ) Standby: 1.5 W (Typ) Completely static memory. No clock or timing strobe required Equal access and cycle times Common data input and output. Three state output Battery backup operation. 2 chip selection for battery backup Temperature range: -40 to +85C
* * * * *
HM62V8100I Series
Ordering Information
Type No. HM62V8100LTTI-5 HM62V8100LTTI-5SL HM62V8100LBPI-5 HM62V8100LBPI-5SL Access time 55 ns 55 ns 55 ns 55 ns 48-bumps CSP with 0.75 mm bump pitch (TBP-48A) Package 400-mil 44pin plastic TSOP II (normal-bend type) (TTP-44DE)
2
HM62V8100I Series
Pin Arrangement
44-pin TSOP A4 A3 A2 A1 A0 CS1 NC NC I/O0 I/O1 VCC VSS I/O2 I/O3 NC NC WE A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 (Top view) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE CS2 A8 NC NC I/O7 I/O6 VSS VCC I/O5 I/O4 NC NC A9 A10 A11 A12 A13 A14
Pin Description (TSOP)
Pin name A0 to A19 I/O0 to I/O7 CS1 CS2 WE OE VCC VSS NC Function Address input Data input/output Chip select 1 Chip select 2 Write enable Output enable Power supply Ground No connection
3
HM62V8100I Series
48-bumps CSP
1 A
NC
2
OE
3
A0
4
A1
5
A2
6
CS2
B
NC
NC
A3
A4
CS1
NC
C
I/O0
NC
A5
A6
NC
I/O4
D
VSS
I/O1
A17
A7
I/O5
VCC
E
VCC
I/O2
NC
A16
I/O6
VSS
F
I/O3
NC
A14
A15
NC
I/O7
G
NC
NC
A12
A13
WE
NC
H
A18
A8
A9
A10
A11
A19
(Top view)
Pin Description (CSP)
Pin name A0 to A19 I/O0 to I/O7 CS1 CS2 WE OE VCC VSS NC Function Address input Data input/output Chip select 1 Chip select 2 Write enable Output enable Power supply Ground No connection
4
HM62V8100I Series
Block Diagram (TSOP)
LSB V CC V SS
* * * * *
A5 A6 A7 A4 A3 A9 A10 A11 A12 A13 MSB A14
Row decoder
Memory matrix 2,048 x 4,096
I/O0 Input data control I/O7
* *
Column I/O Column decoder
* *
LSB
MSB A16 A17A18 A19 A0 A1 A2 A15A8
* *
CS2 CS1 Control logic WE OE
5
HM62V8100I Series
Block Diagram (CSP)
LSB V CC V SS
* * * * *
A6 A15 A11 A16 A7 A13 A10 A2 A4 A1 MSB A3
Row decoder
Memory matrix 2,048 x 4,096
I/O0 Input data control I/O7
* *
Column I/O Column decoder
* *
LSB
MSB A12 A9 A18 A8 A14 A17 A5A0A19
* *
CS2 CS1 Control logic WE OE
6
HM62V8100I Series
Operation Table
CS1 H x L L L CS2 x L H H H WE x x H L H OE x x L x H I/O0 to I/O7 High-Z High-Z Dout Din High-Z Operation Standby Standby Read Write Output disable
Note: H: V IH, L: VIL, x: VIH or VIL
Absolute Maximum Ratings
Parameter Power supply voltage relative to V SS Terminal voltage on any pin relative to V SS Power dissipation Storage temperature range Storage temperature range under bias Symbol VCC VT PT Tstg Tbias Value -0.5 to + 4.6 -0.5* to V CC + 0.3* 1.0 -55 to +125 -40 to +85
1 2
Unit V V W C C
Notes: 1. VT min: -3.0 V for pulse half-width 30 ns. 2. Maximum voltage is +4.6 V.
DC Operating Conditions
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Ambient temperature range Note: VIH VIL Ta Min 2.7 0 2.2 -0.3 -40 Typ 3.0 0 -- -- -- Max 3.6 0 VCC + 0.3 0.6 85 Unit V V V V C 1 Note
1. VIL min: -3.0 V for pulse half-width 30 ns.
7
HM62V8100I Series
DC Characteri stics
Parameter Input leakage current Output leakage current Symbol Min |ILI| |ILO | -- -- Typ* 1 Max -- -- 1 1 Unit A A Test conditions Vin = VSS to V CC CS1 = VIH or CS2 = VIL or OE = VIH or WE = VIL, or VI/O = VSS to V CC CS1 = VIL, CS2 = VIH, Others = VIH/VIL, I I/O = 0 mA Min. cycle, duty = 100%, I I/O = 0 mA, CS1 = VIL, CS2 = VIH, Others = VIH/VIL Cycle time = 1 s, duty = 100%, I I/O = 0 mA, CS1 0.2 V, CS2 V CC - 0.2 V VIH V CC - 0.2 V, VIL 0.2 V CS2 = VIL 0 V Vin (1) 0 V CS2 0.2 V or (2) CS1 V CC - 0.2 V, CS2 V CC - 0.2 V
Operating current Average operating current
I CC I CC1
-- --
-- 14
20 25
mA mA
I CC2
--
2
4
mA
Standby current Standby current
I SB I SB1*
2
-- --
0.1 0.5
0.3 25
mA A
I SB1*3 Output high voltage Output low voltage Note: VOH VOL
-- 2.2 --
0.5 -- --
10 -- 0.4
A V V I OH = -1 mA I OL = 2 mA
1. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. 2. This characteristic is guaranteed only for L version. 3. This characteristic is guaranteed only for L-SL version.
Capacitance (Ta = +25C, f = 1.0 MHz)
Parameter Input capacitance Input/output capacitance Note: Symbol Cin CI/O Min -- -- Typ -- -- Max 8 10 Unit pF pF Test conditions Vin = 0 V VI/O = 0 V Note 1 1
1. This parameter is sampled and not 100% tested.
8
HM62V8100I Series
AC Characteristics (Ta = -40 to +85C, VCC = 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions * * * * Input pulse levels: VIL = 0.4 V, VIH = 2.2 V Input rise and fall time: 5 ns Input and output timing reference levels: 1.5 V Output load: See figures (Including scope and jig)
VTM
R1 Dout R1 = 3070 30pF R2 R2 = 3150 VTM = 2.8 V
9
HM62V8100I Series
Read Cycle
HM62V8100I -5 Parameter Read cycle time Address access time Chip select access time Symbol t RC t AA t ACS1 t ACS2 Output enable to output valid Output hold from address change Chip select to output in low-Z t OE t OH t CLZ1 t CLZ2 Output enable to output in low-Z Chip deselect to output in high-Z t OLZ t CHZ1 t CHZ2 Output disable to output in high-Z t OHZ Min 55 -- -- -- -- 10 10 10 5 0 0 0 Max -- 55 55 55 35 -- -- -- -- 20 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns 2, 3 2, 3 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 Notes
10
HM62V8100I Series
Write Cycle
HM62V8100I -5 Parameter Write cycle time Address valid to end of write Chip selection to end of write Write pulse width Address setup time Write recovery time Data to write time overlap Data hold from write time Output active from end of write Output disable to output in High-Z Write to output in high-Z Symbol t WC t AW t CW t WP t AS t WR t DW t DH t OW t OHZ t WHZ Min 55 50 50 40 0 0 25 0 5 0 0 Max -- -- -- -- -- -- -- -- -- 20 20 Unit ns ns ns ns ns ns ns ns ns ns ns 2 1, 2 1, 2 5 4 6 7 Notes
Notes: 1. t CHZ, tOHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperature and voltage condition, t HZ max is less than tLZ min both for a given device and from device to device. 4. A write occures during the overlap of a low CS1, a high CS2, a low WE. A write begins at the latest transition among CS1 going low, CS2 going high, WE going low. A write ends at the earliest transition among CS1 going high, CS2 going low, WE going high. tWP is measured from the beginning of write to the end of write. 5. t CW is measured from the later of CS1 going low or CS2 going high to the end of write. 6. t AS is measured from the address valid to the beginning of write. 7. t WR is measured from the earliest of CS1 or WE going high or CS2 going low to the end of write cycle.
11
HM62V8100I Series
Timing Waveform
Read Cycle
t RC Address tAA tACS1 CS1 tCLZ1*2, 3 tCHZ1 1, 2, 3 * Valid address
CS2
tACS2 tCLZ2*2, 3 tCHZ2*1, 2, 3 tOHZ*1, 2, 3 tOE
OE tOLZ*2, 3 Dout High impedance Valid data tOH
12
HM62V8100I Series
Write Cycle (1) (WE Clock)
tWC Address Valid address tWR*7
tCW*5 CS1 tCW*5 CS2
tAW tWP*4
WE
tAS*6 tDW tDH
Din tWHZ*1, 2
Valid data tOW*2 High impedance
Dout
13
HM62V8100I Series
Write Cycle (2) (CS Clock, OE = VIH)
tWC Address Valid address tAW tAS*6 CS1 tCW*5 CS2 tWP*4 WE tDW Din Valid data tDH tCW*5 tWR*7
High impedance Dout
14
HM62V8100I Series
Low VCC Data Retention Characteristics (Ta = -40 to +85C)
Parameter VCC for data retention Symbol VDR Min 2.0 Typ* 4 -- Max 3.6 Unit V Test conditions*3 Vin 0V (1) 0 V CS2 0.2 V or (2) CS2 V CC - 0.2 V CS1 V CC - 0.2 V VCC = 3.0 V, Vin 0V (1) 0 V CS2 0.2 V or (2) CS2 V CC - 0.2 V, CS1 V CC - 0.2 V
Data retention current
I CCDR*1
--
0.5
25
A
I CCDR*2 Chip deselect to data retention time Operation recovery time t CDR tR
-- 0 t RC* 5
0.5 -- --
10 -- --
A ns ns See retention waveform
Notes: 1. This characteristic is guaranteed only for L version. 2. This characteristic is guaranteed only for L-SL version. 3. CS2 controls address buffer, WE buffer, CS1 buffer, OE buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE, OE, CS1, I/O) can be in the high impedance state. If CS1 controls data retention mode, CS2 must be CS2 V CC - 0.2 V or 0 V CS2 0.2 V. The other input levels (address, WE, OE, I/O) can be in the high impedance state. 4. Typical values are at VCC = 3.0 V, Ta = +25C and not guaranteed. 5. t RC = read cycle time.
15
HM62V8100I Series
Low V CC Data Retention Timing Waveform (1) (CS1 Controlled)
Data retention mode tR
t CDR VCC 2.7 V
2.2 V VDR CS1 0V CS1 VCC - 0.2 V
Low V CC Data Retention Timing Waveform (2) (CS2 Controlled)
t CDR VCC 2.7 V CS2 VDR 0.6 V 0V 0 V < CS2 < 0.2 V Data retention mode tR
16
HM62V8100I Series
Package Dimensions
HM62V8100LTTI Series (TTP-44DE)
As of July, 2001
18.41 18.81 Max 44 23
Unit: mm
1 *0.27 0.07 0.25 0.05
0.80 0.13 M
22 0.80
10.16
1.005 Max *0.145 0.05 0.125 0.04
11.76 0.20 0.50 0.10 0.68 0 - 5 0.13 0.05
1.20 Max
0.10
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC JEITA Mass (reference value)
TTP-44DE -- -- 0.43 g
17
HM62V8100I Series
HM62V8100LBPI Series (TBP-48A)
As of July, 2001
Unit: mm
0.20 S B
0.20 S A
2.275
6.50
A
6 5 4 3
A 2 1
INDEX MARK
Pin#1 INDEX
A B C B
9.80
D E F G 0.75 H
4x
0.15
0.75
1.375
0.2 S
S
48 x 0.35 0.05 0.08 M S A B
0.25 0.05
0.10 S
1.2 Max
Details of the part A
Hitachi Code JEDEC JEITA Mass (reference value)
TBP-48A - - 0.13 g
18
HM62V8100I Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109
URL
http://www.hitachisemiconductor.com/
For further information write to:
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 585200 Hitachi Europe GmbH Electronic Components Group Dornacher Strae 3 D-85622 Feldkirchen Postfach 201,D-85619 Feldkirchen Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-538-6533/538-8577 Fax : <65>-538-6933/538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://www.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-(2)-735-9218 Fax : <852>-(2)-730-0281 URL : http://semiconductor.hitachi.com.hk
Copyright (c) Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.
Colophon 5.0
19

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